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(parent: d9a4381) | patch
Support for SystemVerilog interfaces as a port in the top level module + test case
authorRuben Undheim <ruben.undheim@gmail.com>
Sat, 20 Oct 2018 09:58:25 +0000 (11:58 +0200)
committerRuben Undheim <ruben.undheim@gmail.com>
Sat, 20 Oct 2018 09:58:25 +0000 (11:58 +0200)
commit397dfccb304a12a40d34c4454a5cb4acee8be75f
tree39f2bdcbfbc62de55f7333c0bcfb509735bf561atree
parentd9a438101298710b9dadd4e7a1cb0041e8ba4199commit | diff
Support for SystemVerilog interfaces as a port in the top level module + test case
frontends/ast/ast.cc diff | blob | history
passes/hierarchy/hierarchy.cc diff | blob | history
tests/svinterfaces/run-test.sh diff | blob | history
tests/svinterfaces/runone.sh diff | blob | history
tests/svinterfaces/svinterface_at_top.sv [new file with mode: 0644] blob
tests/svinterfaces/svinterface_at_top_ref.v [new file with mode: 0644] blob
tests/svinterfaces/svinterface_at_top_tb.v [new file with mode: 0644] blob
tests/svinterfaces/svinterface_at_top_tb_wrapper.v [new file with mode: 0644] blob
tests/svinterfaces/svinterface_at_top_wrapper.v [new file with mode: 0644] blob