More explicit integer output in verilog backend
authorClifford Wolf <clifford@clifford.at>
Thu, 22 Aug 2013 18:22:19 +0000 (20:22 +0200)
committerClifford Wolf <clifford@clifford.at>
Thu, 22 Aug 2013 18:31:04 +0000 (20:31 +0200)
commit39ee561169ba04374c2c630a5ef5a61537a67c13
tree8b70b654407178a08dc51eb5b99a007b00a9dc96
parent4f4cb2307f8405f25e62cea264ebf20973ab30b1
More explicit integer output in verilog backend
backends/verilog/verilog_backend.cc