.gitmodules: use our VexRiscv-verilog
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 26 Apr 2019 21:49:06 +0000 (23:49 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 26 Apr 2019 22:00:55 +0000 (00:00 +0200)
commit3a2e28361350800f9225a0194c968f9f2f755322
treea56d9642dd04a333c782c4b08e6496ded830cd0a
parent78c09125beb53a34c6e44b01a9f7da4afd325d24
.gitmodules: use our VexRiscv-verilog
.gitmodules
litex/soc/cores/cpu/vexriscv/verilog