verilog: add test
authorEddie Hung <eddie@fpgeh.com>
Wed, 11 Mar 2020 13:51:03 +0000 (06:51 -0700)
committerEddie Hung <eddie@fpgeh.com>
Wed, 11 Mar 2020 13:51:03 +0000 (06:51 -0700)
commit3ada82639ffd559da8d3f89664ac279ab2280dae
tree39a3e48d9850e9492342167960b51ba5d11fc18f
parent2d63bf5877a99ad5a83be35b5bdc0702a947d456
verilog: add test
tests/various/src.ys [new file with mode: 0644]