Adding missing vexriscv CPU.
authorTim 'mithro' Ansell <me@mith.ro>
Sun, 23 Feb 2020 22:54:07 +0000 (14:54 -0800)
committerTim 'mithro' Ansell <me@mith.ro>
Sun, 12 Apr 2020 01:37:06 +0000 (18:37 -0700)
commit3ae4f8f2de7494411e5278b11dd7db1c0ae7389f
tree795feb35f1e394ed659fa4ac1b12febf908519a7
parentac3fd794f922061653ace78c59fdeccb4327e178
Adding missing vexriscv CPU.
litex_setup.py