added tests for new verilog features
authorClifford Wolf <clifford@clifford.at>
Sat, 7 Jun 2014 10:18:00 +0000 (12:18 +0200)
committerClifford Wolf <clifford@clifford.at>
Sat, 7 Jun 2014 10:26:11 +0000 (12:26 +0200)
commit3af7c69d1e3c17d7aaa5d3a7da9f8a2ae12ed9bf
tree756e8985a79d7f4d1f93cca435882f5b45eada19
parent744e51846776a304828301914f5cd74fb7d0a5ca
added tests for new verilog features
tests/simple/arraycells.v [new file with mode: 0644]
tests/simple/repwhile.v