git.libre-soc.org Git - yosys.git/commit

author	Clifford Wolf <clifford@clifford.at>
	Sat, 23 Mar 2019 13:38:48 +0000 (14:38 +0100)
committer	Clifford Wolf <clifford@clifford.at>
	Sat, 23 Mar 2019 13:38:48 +0000 (14:38 +0100)
commit	3b796c033cc40a753e24f21b25b2701a30f022f1
tree	237d5e489e8c996061cfaed1e716a704cb9a08b7	tree
parent	a440f82586eda461ae2a90cba7a14d7078c41f37	commit \| diff

Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals

Signed-off-by: Clifford Wolf <clifford@clifford.at>

kernel/rtlil.cc		diff \| blob \| history
kernel/rtlil.h		diff \| blob \| history