Support optional labels at the end of module definition
authorLukasz Dalek <ldalek@antmicro.com>
Tue, 19 May 2020 14:58:48 +0000 (16:58 +0200)
committerKamil Rakoczy <krakoczy@antmicro.com>
Wed, 24 Jun 2020 09:57:45 +0000 (11:57 +0200)
commit3b81a1b80926138cf0c3fe6d88818b689be3121c
treebd603d80da1343ef796c97c69e610bd6c73c568b
parent0835a86e30fc2a934f5e6c96b28c90b59654ed92
Support optional labels at the end of module definition

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
frontends/verilog/verilog_parser.y