Fixed bug in $mem cell verilog code generation.
authorluke whittlesey <luke.whittlesey@gmail.com>
Mon, 11 May 2015 18:05:18 +0000 (14:05 -0400)
committerluke whittlesey <luke.whittlesey@gmail.com>
Mon, 11 May 2015 18:05:18 +0000 (14:05 -0400)
commit3bb5f064b872e6e313d66e2d34e431da032f6938
tree5f36ddc7e967dc5dc7561e7266580d378e6aa128
parente47218e9ea678b705cb79e687fa88d8afb2ced4e
Fixed bug in $mem cell verilog code generation.
backends/verilog/verilog_backend.cc