Merge pull request #953 from YosysHQ/clifford/fix948
authorClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 18:01:09 +0000 (20:01 +0200)
committerGitHub <noreply@github.com>
Mon, 22 Apr 2019 18:01:09 +0000 (20:01 +0200)
commit3be5aac52c8703aa00ff591fd184da1ac39df678
tree1b9a402b5151ffb19b85287b4989489ce5c7a77d
parent9050b5e1915b05f55c1db279566f34202905f02a
parent0e0c80fac883a6f512a94aecdc3c915b8cacb562
Merge pull request #953 from YosysHQ/clifford/fix948

Add support for zero-width signals to Verilog back-end