[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.

[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.

Include a new iclass to extract the variant from the most significant 3
bits of this operand.

Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.

The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.

gas/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
	operand.

include/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
	operand.
	(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.

opcodes/ChangeLog:

2019-05-09  Matthew Malcomson  <matthew.malcomson@arm.com>

	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.
	* aarch64-asm.c (aarch64_ins_sve_shrimm):
	(aarch64_encode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass encode.
	* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
	sve_shift_tsz_hsd iclass decode.
	* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
	for SVE_SHRIMM_UNPRED_22.
	(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
	* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
	operand.