i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination

i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination

FROM_DOUBLE opcodes are setup so that they use a dst register
with a size of 2 even if they only produce a single-precison
result (this is so that the opcode can use the larger register to
produce a 64-bit aligned intermediary result as required by the
hardware during the conversion process). This creates a problem for
spilling though, because when we attempt to emit a spill for the
dst we see a 32-bit destination and emit a scratch write that
allocates a single spill register, making the intermediary writes
go beyond the size of the allocation.

Prevent this by avoiding to spill the destination register of these
opcodes.

Alternatively, we can avoid this by splitting the opcode in two: one
that produces a 64-bit aligned result and one that takes the 64-bit
aligned result as input and produces a 32-bit result from it.

Reviewed-by: Matt Turner <mattst88@gmail.com>