Regression: Use addTwoLevelCacheHierarchy in configs
authorAndreas Hansson <andreas.hansson@arm.com>
Mon, 15 Oct 2012 12:07:09 +0000 (08:07 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Mon, 15 Oct 2012 12:07:09 +0000 (08:07 -0400)
commit3cf733bcc07b0a8bf069f8581b7f3902bc38f0e0
tree8513d98d2e8d19c0742084a5fa2f9e9930aa1367
parent930db9257dbac7e678888a65a17c39bcc87aa7fa
Regression: Use addTwoLevelCacheHierarchy in configs

This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.

The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.

The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.
tests/configs/pc-o3-timing.py
tests/configs/pc-simple-atomic.py
tests/configs/pc-simple-timing.py
tests/configs/realview-o3-checker.py
tests/configs/realview-o3.py
tests/configs/realview-simple-atomic.py
tests/configs/realview-simple-timing.py
tests/configs/tsunami-inorder.py
tests/configs/tsunami-o3.py
tests/configs/tsunami-simple-atomic.py
tests/configs/tsunami-simple-timing.py