back.rtlil: implement memories.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)
commit3d26ed0bdccd989be888832b6b9f827dceca6c56
treec21f79228964f9d84e0a6c7afbb1f2d1dd5c0bea
parent341dcc48410a786ead4e65d880bb356f92554689
back.rtlil: implement memories.
examples/mem.py [new file with mode: 0644]
nmigen/back/rtlil.py
nmigen/back/verilog.py