Merge pull request #513 from udif/pr_reg_wire_error
authorClifford Wolf <clifford@clifford.at>
Wed, 15 Aug 2018 11:35:41 +0000 (13:35 +0200)
committerGitHub <noreply@github.com>
Wed, 15 Aug 2018 11:35:41 +0000 (13:35 +0200)
commit3d27c1cc80da1c631bf5eb9c0b6b27e74ca73873
tree571f3835d5202c2540eed44b342ff187a65ce13b
parentd71529baa1deb224ab520b2431b2c1a176170054
parent73d426bc879087ca522ca595a8ba921b647fae27
Merge pull request #513 from udif/pr_reg_wire_error

Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/simplify.cc
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y