add input and output reset signals to Pin

add input and output reset signals to Pin
https://gitlab.com/nmigen/nmigen/-/issues/2

the issue being encountered is that ECP5 2x, 4x and 7x phase-tapped
IO pads will come up 50% of the time in an incorrect phase
setting the RST line of IDDR71B and other IOpad instances to Const(0)
is the likely root cause.

unfortunately, to fix this, an actual Signal has to be passed in,
to the LatticeECP5Platform, for it to be able to pass it to the IOpad.
that in turn means that the Pin Record has to have a reset signal added.

current experiments with GRAM show that setting the reset signal equal
to the domain reset signal is not quite sufficient, but greatly improves
the number of times that the DQS and other DDR IOpads get a successful
lock.  this most likely because the 2x PLL has not been given enough
time to stabilise.  at least with the addition of reset signals
i_prst and o_prst to Pin, experimentation and investigation can proceed