RISC-V: Fix disassembling Zfinx with -M numeric
authorTsukasa OI <research_trasio@irq.a4lg.com>
Mon, 27 Jun 2022 02:03:44 +0000 (11:03 +0900)
committerNelson Chu <nelson.chu@sifive.com>
Thu, 7 Jul 2022 04:06:02 +0000 (12:06 +0800)
commit3d5d6bd55433735c4fc620a47b543065582d06ae
tree7de69e8d4565d68c1eda18aaae0ac7185abf36d3
parent37cf60c6a6d36bbf5cf1523697906c4bdb4eb468
RISC-V: Fix disassembling Zfinx with -M numeric

This commit fixes floating point operand register names from ABI ones
to dynamically set ones.

gas/ChangeLog:

* testsuite/gas/riscv/zfinx-dis-numeric.s: Test new behavior of
Zfinx extension and -M numeric disassembler option.
* testsuite/gas/riscv/zfinx-dis-numeric.d: Likewise.

opcodes/ChangeLog:

* riscv-dis.c (riscv_disassemble_insn): Use dynamically set GPR
names to disassemble Zfinx instructions.
gas/testsuite/gas/riscv/zfinx-dis-numeric.d [new file with mode: 0644]
gas/testsuite/gas/riscv/zfinx-dis-numeric.s [new file with mode: 0644]
opcodes/riscv-dis.c