projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Thu, 3 Nov 2016 11:13:23 +0000 (12:13 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Thu, 3 Nov 2016 11:13:23 +0000 (12:13 +0100) | ||
| commit | 3db2ac4e0036d5ebdc0d81eb61ae0241a18f7c6f | |
| tree | 9dc7bcf109c5de545221c440a9dd4e7d2cd9a6f4 | tree |
| parent | e3330fb98f80c7cbd233bc1bb8e49bc8b4d27bab | commit | diff |
| backends/verilog/verilog_backend.cc | diff | blob | history | |
| techlibs/gowin/synth_gowin.cc | diff | blob | history |