Add dynamic slicing Verilog testcase
authorEddie Hung <eddie@fpgeh.com>
Tue, 31 Mar 2020 18:51:31 +0000 (11:51 -0700)
committerEddie Hung <eddie@fpgeh.com>
Tue, 31 Mar 2020 18:51:31 +0000 (11:51 -0700)
commit3df66027e0de11913aac4b29d6b4ab79550bfb28
treea6b765abd56b972c4277524c70ee474aec8e4d03
parenta0cc795e85541b0326b6d4396a726142f0d0f8bb
Add dynamic slicing Verilog testcase
tests/simple/dynslice.v [new file with mode: 0644]