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(parent: aedbb0f) | patch
back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.
authorwhitequark <whitequark@whitequark.org>
Sun, 25 Oct 2020 01:59:46 +0000 (01:59 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 15:16:10 +0000 (15:16 +0000)
commit3e167f73d3510cccdea81b86bcb1b33e7be0cc2a
tree5d3513f0db6f27b0cced69fa7f0d7cb6844676fdtree
parentaedbb0fa7f969ea353fd0d7bd489260beb6656fbcommit | diff
back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.

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nmigen/back/rtlil.py diff | blob | history
nmigen/back/verilog.py diff | blob | history