xilinx/common: be sure language is not vhdl when yosys synthesis is used
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 7 Oct 2019 08:36:32 +0000 (10:36 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 7 Oct 2019 08:36:32 +0000 (10:36 +0200)
commit3e22d4b9e610d792b75bfaf2e1da42f93d91d33a
tree38e5efafb30f7b2ad1d75442e49edf8242d0054a
parent975bd9be8bc0f44fc24b8249ed20010610ee7f46
xilinx/common: be sure language is not vhdl when yosys synthesis is used
litex/build/xilinx/common.py