[AArch64][1/2] Fix offset glitch in load reg pair pattern

[AArch64][1/2] Fix offset glitch in load reg pair pattern

on aarch64, we are using load register pair post-writeback instruction in
epilogue.

for example, for the following instruction:

ldp, x0, x1, [sp], #16

what it's doing is:

x0 <- MEM(sp + 0)
x1 <- MEM(sp + 8)
sp < sp + 16

while there is a glitch in our loadwb_pair* pattern, the restore of the
first reg should always be with offset zero.

(set (match_operand:GPI 2 "register_operand" "=r")
-          (mem:GPI (plus:P (match_dup 1)
-                   (match_dup 4))))
+          (mem:GPI (match_dup 1)))

gcc/
  * config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix offset.
  (loadwb_pair<GPI:mode>_<P:mode>): Likewise.
  * config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): Likewise.

From-SVN: r213485