[AArch64] Fix lane specifier syntax
authorWilco Dijkstra <wdijkstr@arm.com>
Fri, 6 Mar 2020 18:19:46 +0000 (18:19 +0000)
committerWilco Dijkstra <wdijkstr@arm.com>
Fri, 6 Mar 2020 18:19:46 +0000 (18:19 +0000)
commit3e5c062e96c11a6eaef1cbf94b5992391a850dbf
tree7c9ddb6920bd973b8893e4d8ee09c90032875f89
parent4a5c938bbfd4586f16ff0dfde00970c2a1b0f636
[AArch64] Fix lane specifier syntax

The syntax for lane specifiers uses a vector element rather than a vector:

fmls    v0.2s, v1.2s, v1.s[1]  // rather than v1.2s[1]

Fix all the lane specifiers to use Vetype which uses the correct element type.

    gcc/
* aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): Correct lane syntax.
(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
(aarch64_mls_elt<mode>): Likewise.
(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt<mode>): Likewise.
(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fma4_elt_to_64v2df): Likewise.
(aarch64_fnma4_elt<mode>): Likewise.
(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
(aarch64_fnma4_elt_to_64v2df): Likewise.

    testsuite/
* gcc.target/aarch64/fmla_intrinsic_1.c: Check for correct lane syntax.
* gcc.target/aarch64/fmls_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mla_intrinsic_1.c: Likewise.
* gcc.target/aarch64/mls_intrinsic_1.c: Likewise.
gcc/ChangeLog
gcc/config/aarch64/aarch64-simd.md
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/aarch64/fmla_intrinsic_1.c
gcc/testsuite/gcc.target/aarch64/fmls_intrinsic_1.c
gcc/testsuite/gcc.target/aarch64/mla_intrinsic_1.c
gcc/testsuite/gcc.target/aarch64/mls_intrinsic_1.c