r300/compiler: Fix instruction scheduling within IF blocks

r300/compiler: Fix instruction scheduling within IF blocks

Reads of registers that where not written to within the same block were
not being tracked.  So in a situations like this:
0: IF
1: ADD t0, t1, t2
2: MOV t2, t1

Instruction 2 didn't know that instruction 1 read from t2, so
in some cases instruction 2 was being scheduled before instruction 1.

NOTE: This is a candidate for the 7.9 branch.