[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>
authorJames Greenhalgh <james.greenhalgh@arm.com>
Thu, 31 Aug 2017 16:03:09 +0000 (16:03 +0000)
committerJames Greenhalgh <jgreenhalgh@gcc.gnu.org>
Thu, 31 Aug 2017 16:03:09 +0000 (16:03 +0000)
commit3ec5b5f015903512558b480752056ac9e41e8f3d
tree4b81afe9c0409697be8e864ed176820f5a074a50
parentb54d4018b17c8e7be96cedd211e7c9dd5d1c3e43
[AArch64 obvious] Fix register constraints for aarch64_ml[as]_elt_merge<mode>

The MLA by-element instructions have the same restriction as other by-element
instructions whereby the forms operating on vectors of 16-bit integer data
may only use registers v0-v15. We have an iterator for that, applied to the
other patterns generating this instruction, so use that.

gcc/

* config/aarch64/aarch64-simd.md (aarch64_mla_elt_merge<mode>): Fix
register constraint for by-element operand.
(aarch64_mls_elt_merge<mode>): Likewise.

From-SVN: r251568
gcc/ChangeLog
gcc/config/aarch64/aarch64-simd.md