power: Add power states to ClockedObject
authorAkash Bagdia <akash.bagdia@ARM.com>
Tue, 18 Nov 2014 14:00:48 +0000 (14:00 +0000)
committerAkash Bagdia <akash.bagdia@ARM.com>
Tue, 18 Nov 2014 14:00:48 +0000 (14:00 +0000)
commit3ee4957b4930a252c0185a6bc71bdf1c6ebc5ed9
tree6a7e1807397f002f51fddb34568b89250fca45c8
parent65ecd954861aa76532ca79453afcf66a837e1fa6
power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.
24 files changed:
src/arch/alpha/tlb.cc
src/arch/mips/tlb.cc
src/arch/power/tlb.cc
src/cpu/testers/memtest/memtest.cc
src/dev/arm/flash_device.cc
src/dev/arm/hdlcd.cc
src/dev/arm/ufs_device.cc
src/mem/probes/stack_dist.cc
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc
src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
src/mem/ruby/network/simple/SimpleNetwork.cc
src/mem/ruby/network/simple/Switch.cc
src/mem/ruby/slicc_interface/AbstractController.cc
src/mem/ruby/structures/CacheMemory.cc
src/mem/ruby/structures/Prefetcher.cc
src/mem/ruby/system/RubySystem.hh
src/mem/ruby/system/Sequencer.cc
src/mem/snoop_filter.cc
src/sim/ClockedObject.py
src/sim/SConscript
src/sim/clock_domain.cc
src/sim/clocked_object.cc [new file with mode: 0644]
src/sim/clocked_object.hh
src/sim/voltage_domain.cc