back.pysim: new simulator backend (WIP).
authorwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 18:00:05 +0000 (18:00 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 13 Dec 2018 18:02:46 +0000 (18:02 +0000)
commit3eed2ef6c8b9da8e48ed1da151091c0e114ee5cb
tree4e768a9625339f9a7739dc8da7000f1e21cdb7da
parent36f465e26455168f357c63fbfc2f456034031f3c
back.pysim: new simulator backend (WIP).
.gitignore
examples/clkdiv.py
nmigen/back/pysim.py [new file with mode: 0644]
nmigen/fhdl/ast.py
nmigen/fhdl/ir.py
nmigen/test/test_fhdl_dsl.py
nmigen/test/test_fhdl_value.py
nmigen/test/test_fhdl_xfrm.py
setup.py