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(parent: af52203) | patch
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
authorGabriel Somlo <gsomlo@gmail.com>
Sun, 17 Nov 2019 15:08:50 +0000 (10:08 -0500)
committerGabriel Somlo <gsomlo@gmail.com>
Mon, 18 Nov 2019 14:00:19 +0000 (09:00 -0500)
commit3ef13fd27a027c98bbe2a0b5b252c175fc0262c6
treeedec1fa8cb5a9db0e152d7a7edc9ca42c52a54betree
parentaf52203c003cb1cf1aa67fc30c21466545fcd10ccommit | diff
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32

Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.

Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
litex/soc/integration/soc_sdram.py diff | blob | history
litex/soc/software/bios/sdram.c diff | blob | history