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(parent: 4824867) | patch
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 13 Apr 2015 19:47:55 +0000 (21:47 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 13 Apr 2015 19:47:55 +0000 (21:47 +0200)
commit3f15699964e82054b4261a5100ce4fbce8a5e0dc
tree1e413515f9bc23e8237b79fa8c572e94fcddf191tree
parent482486706ccf1ee2fb94348a317879a7a6bc1b6bcommit | diff
revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue)
migen/fhdl/verilog.py diff | blob | history