i965/nir: Replace fs_reg(GRF, virtual_grf_alloc(...)) with vgrf(...).

i965/nir: Replace fs_reg(GRF, virtual_grf_alloc(...)) with vgrf(...).

brw_fs_nir.cpp creates almost all of its registers via:

   fs_reg reg = fs_reg(GRF, virtual_grf_alloc(num_components));

When we add SIMD16 support, we'll need to set reg->width = 16 and
double the VGRF size...on pretty much every VGRF it allocates.

This patch replaces that pattern with a new "vgrf" helper method:

   fs_reg reg = vgrf(num_components);

The new function correctly takes reg_width into account.  For now,
reg_width is always 1, so this should have no functional change.

v2: Just make vgrf() account for reg_width right away, rather than
    changing the behavior in the next patch.

v3: Replace one last virtual_grf_alloc I missed.  It's used in code
    that only runs for dispatch_width == 8, so it doesn't matter,
    but consistency is nice.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>