arch-riscv: Remove static parts of AMOs out of ISA
authorAlec Roelke <ar4jc@virginia.edu>
Fri, 10 Nov 2017 17:23:43 +0000 (12:23 -0500)
committerAlec Roelke <ar4jc@virginia.edu>
Wed, 29 Nov 2017 01:05:24 +0000 (01:05 +0000)
commit3f31abfbc84734dab86734c72bdca778575c26e5
treeab5e7c74b35c90c43c79cd5d40ba1f2751bbd05a
parent719ddf73afa62735881ac68acf681abe1bf3bd17
arch-riscv: Remove static parts of AMOs out of ISA

This patch removes the static parts of the RISC-V atomic memory
instructions out of the ISA generated code and into arch/riscv/insts. It
also makes the LR and SC instructions subclasses of MemInst from
arch/riscv/insts/mem.hh.

Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51
Reviewed-on: https://gem5-review.googlesource.com/6025
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>
src/arch/riscv/insts/SConscript
src/arch/riscv/insts/amo.cc [new file with mode: 0644]
src/arch/riscv/insts/amo.hh [new file with mode: 0644]
src/arch/riscv/isa/formats/amo.isa
src/arch/riscv/isa/includes.isa