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author	Ali Saidi <Ali.Saidi@ARM.com>
	Fri, 13 May 2011 22:27:01 +0000 (17:27 -0500)
committer	Ali Saidi <Ali.Saidi@ARM.com>
	Fri, 13 May 2011 22:27:01 +0000 (17:27 -0500)
commit	401165c778108ab22aeeee55c4f4451ca93bcffb
tree	f525ba64108f6ebe208a04d2dee7b77621cafd96	tree
parent	e097c4fb188fafc9cd2253500ab2d056da886c9c	commit \| diff

ARM: Further break up condition code into NZ, C, V bits.

Break up the condition code bits into NZ, C, V registers. These are individually
written and this removes some incorrect dependencies between instructions.

18 files changed:

src/arch/arm/faults.cc		diff \| blob \| history
src/arch/arm/intregs.hh		diff \| blob \| history
src/arch/arm/isa/formats/fp.isa		diff \| blob \| history
src/arch/arm/isa/formats/pred.isa		diff \| blob \| history
src/arch/arm/isa/insts/data.isa		diff \| blob \| history
src/arch/arm/isa/insts/fp.isa		diff \| blob \| history
src/arch/arm/isa/insts/ldr.isa		diff \| blob \| history
src/arch/arm/isa/insts/macromem.isa		diff \| blob \| history
src/arch/arm/isa/insts/mem.isa		diff \| blob \| history
src/arch/arm/isa/insts/misc.isa		diff \| blob \| history
src/arch/arm/isa/insts/mult.isa		diff \| blob \| history
src/arch/arm/isa/insts/str.isa		diff \| blob \| history
src/arch/arm/isa/operands.isa		diff \| blob \| history
src/arch/arm/isa/templates/pred.isa		diff \| blob \| history
src/arch/arm/isa/templates/vfp.isa		diff \| blob \| history
src/arch/arm/miscregs.hh		diff \| blob \| history
src/arch/arm/nativetrace.cc		diff \| blob \| history
src/arch/arm/utility.hh		diff \| blob \| history