cores/clock: add divclk_divide_range on S6PLL/S6DCM
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 23 Apr 2019 04:43:48 +0000 (06:43 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 23 Apr 2019 04:43:48 +0000 (06:43 +0200)
commit40342404f2ca4f55a65aaf98949b8459c49b01b0
tree2d0d9a320c34d9d410c2035d45e8f4ded248982e
parent0d282f38f914fdab4d4945c0c5622b315fddf700
cores/clock: add divclk_divide_range on S6PLL/S6DCM
litex/soc/cores/clock.py