RISC-V: Add stub support for the 'Svadu' extension
authorTsukasa OI <research_trasio@irq.a4lg.com>
Mon, 24 Oct 2022 15:05:58 +0000 (15:05 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 5 Sep 2023 04:57:09 +0000 (04:57 +0000)
commit404def8928b5746573e24dc31c6fd6ec5b07d97f
tree870c1f8728b0e372c6f3ae9a63b33c43d61d73bf
parent2a546455f456ad190e8c4785fd2b170659bf2236
RISC-V: Add stub support for the 'Svadu' extension

This commit implements support for 'Svadu' extension.  Because it does not
add any instructions or CSRs (but adds bits to existing CSRs), this commit
only adds extension name support and implication to the 'Zicsr' extension.

This is based on the "Hardware Updating of PTE A/D Bits (Svadu)"
specification, version 1.0-rc1 (Frozen):
<https://github.com/riscv/riscv-svadu/releases/tag/v1.0-rc1>

bfd/ChangeLog:

* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
bfd/elfxx-riscv.c