X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
authorGabe Black <gblack@eecs.umich.edu>
Tue, 23 Nov 2010 11:11:50 +0000 (06:11 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Tue, 23 Nov 2010 11:11:50 +0000 (06:11 -0500)
commit40d434d5516affffe9ded9365e0d2da060aa7c78
tree095a480b2f025a4e113d09b693a6cb3c7ccf2040
parent3cd349f44305d6ca9496f7f626f0f4f939bd84ad
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
src/cpu/BaseCPU.py