Implemented $_DFFSR_ expression generator in verilog backend
authorClifford Wolf <clifford@clifford.at>
Thu, 21 Nov 2013 20:52:30 +0000 (21:52 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 21 Nov 2013 20:52:30 +0000 (21:52 +0100)
commit40d9542647420e16d7980eeb917e3f2387b1f399
tree2e76389c1160239c4982bc54483923cbc5ad6963
parent95c94a02fc55664b5895f95e54a7212213539068
Implemented $_DFFSR_ expression generator in verilog backend
backends/verilog/verilog_backend.cc