vexriscv_debug: use csr read()/write() accessors
authorSean Cross <sean@xobs.io>
Tue, 17 Jul 2018 10:03:58 +0000 (18:03 +0800)
committerSean Cross <sean@xobs.io>
Tue, 17 Jul 2018 10:03:58 +0000 (18:03 +0800)
commit41a9e7d9aebbfcece57b7e375a39ba8e1ff3107a
tree2fa7d2512a1f3e44746acef04fca25eb99c9680c
parentf9104b201a17ec22586a39950f4de5a5904e9fcb
vexriscv_debug: use csr read()/write() accessors

CSR access widths can be different from register widths.  8-bit
registers are common.

The runtime-generated `read()` and `write()` functions handle this
mapping correctly.  When direct register accesses are handled, this
mapping is lost.

Use the accessor functions rather than directly accessing the memory
addresses, so that we work on platforms other than 32-bit-wide.

Signed-off-by: Sean Cross <sean@xobs.io>
litex/soc/tools/vexriscv_debug.py