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(parent: d24a5ea) | patch
completely bungled multi-EXTRA specs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 3 Aug 2022 00:42:10 +0000 (01:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 3 Aug 2022 00:42:10 +0000 (01:42 +0100)
commit43b06b819839a3b84a76fb69a5b3690918e6b381
tree8b27bd367a1916f0e5a93ed8bf5282c07994b935tree
parentd24a5ea2abb11691d88380b48009b1be69344c3acommit | diff
completely bungled multi-EXTRA specs
https://bugs.libre-soc.org/show_bug.cgi?id=838#c9
should be d:RS;d:CR0, missing a semicolon. sigh
openpower/isatables/LDSTRM-2P-2S1D.csv diff | blob | history
openpower/isatables/LDSTRM-2P-3S.csv diff | blob | history
src/openpower/sv/sv_analysis.py diff | blob | history