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(parent: 56fbd2f) | patch
build/sim/modules: add XGMII 10Gbps ethernet module
authorVamsi K Vytla <vkvytla@lbl.gov>
Fri, 15 Nov 2019 09:47:13 +0000 (10:47 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 15 Nov 2019 09:51:55 +0000 (10:51 +0100)
commit446ae57b75ecff6a1ad99457f8d305520ccfcaf0
tree34f19f179f810459506842407f9bcb97405a4c45tree
parent56fbd2f25034e4ee857e12c8f405f95cc739d884commit | diff
build/sim/modules: add XGMII 10Gbps ethernet module

Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
litex/build/sim/core/modules/Makefile diff | blob | history
litex/build/sim/core/modules/xgmii_ethernet/Makefile [new file with mode: 0644] blob
litex/build/sim/core/modules/xgmii_ethernet/tapcfg [new symlink] blob
litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c [new file with mode: 0644] blob
litex/build/sim/verilator.py diff | blob | history