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(parent: 552b024) | patch
soc/interconnect/axi: data/address length cleanup
authorGabriel L. Somlo <gsomlo@gmail.com>
Wed, 27 Mar 2019 20:38:25 +0000 (16:38 -0400)
committerGabriel L. Somlo <gsomlo@gmail.com>
Wed, 27 Mar 2019 20:52:52 +0000 (16:52 -0400)
commit449632e43012bee423c23e634cedf7e3f4ce8696
tree05585bf28182558505383981f7206083798daf5dtree
parent552b0243b398502d6140715139c1739227851b0fcommit | diff
soc/interconnect/axi: data/address length cleanup

Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
litex/soc/interconnect/axi.py diff | blob | history