i965/misc: Use depth/stencil surf's tiling on gen4-5
authorNanley Chery <nanley.g.chery@intel.com>
Mon, 16 Jul 2018 20:03:09 +0000 (13:03 -0700)
committerNanley Chery <nanley.g.chery@intel.com>
Thu, 19 Jul 2018 18:05:07 +0000 (11:05 -0700)
commit44ab26d0c9bd95f8d15ead5b92f743ee13296aef
treeefc37d32d86d1c0c70c0f764d79bb02d8ff6d03f
parent507a8037a731892c1b8cd6e9a8534d4a5447d5c5
i965/misc: Use depth/stencil surf's tiling on gen4-5

Make the 3D engine aware of the depth/stencil surface's tiling before
doing any render operations.

Fixes fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").

Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/brw_misc_state.c