aarch64: Add bfloat16 vldN_lane_bf16 + vldNq_lane_bf16 intrisics

aarch64: Add bfloat16 vldN_lane_bf16 + vldNq_lane_bf16 intrisics

gcc/ChangeLog

2020-10-15  Andrea Corallo  <andrea.corallo@arm.com>

	* config/aarch64/arm_neon.h (__LD2_LANE_FUNC, __LD3_LANE_FUNC)
	(__LD4_LANE_FUNC): Rename the macro generating the 'q' variants
	into __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC, __LD2Q_LANE_FUNC so they
	all can be undefed at the and of the file.
	(vld2_lane_bf16, vld2q_lane_bf16, vld3_lane_bf16, vld3q_lane_bf16)
	(vld4_lane_bf16, vld4q_lane_bf16): Add new intrinsics.

gcc/testsuite/ChangeLog

2020-10-15  Andrea Corallo  <andrea.corallo@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/bf16_vldN_lane_1.c: New
	testcase.
	* gcc.target/aarch64/advsimd-intrinsics/bf16_vldN_lane_2.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld2_lane_bf16_indices_1.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_bf16_indices_1.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld3_lane_bf16_indices_1.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_bf16_indices_1.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld4_lane_bf16_indices_1.c:
	Likewise.
	* gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_bf16_indices_1.c:
	Likewise.