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(parent: 7c69a6d) | patch
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 3 May 2020 19:29:54 +0000 (21:29 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 3 May 2020 19:29:54 +0000 (21:29 +0200)
commit45377d9faa7722c9fb5c8efd9749ecb229d354d3
tree73feacb0244f2889f7d16765264b311e26924bc6tree
parent7c69a6dbba581a57fa9319a9ca4e60882e6f5f1fcommit | diff
cpus: use a common definition of gcc_triple for the RISC-V CPUs, reorganize CPU by ISA/Data-Width.
litex/soc/cores/cpu/__init__.py diff | blob | history
litex/soc/cores/cpu/blackparrot/core.py diff | blob | history
litex/soc/cores/cpu/minerva/core.py diff | blob | history
litex/soc/cores/cpu/picorv32/core.py diff | blob | history
litex/soc/cores/cpu/rocket/core.py diff | blob | history
litex/soc/cores/cpu/serv/core.py diff | blob | history
litex/soc/cores/cpu/vexriscv/core.py diff | blob | history