build,vendor: never carry around parts of differential signals.
authorwhitequark <whitequark@whitequark.org>
Fri, 31 Jul 2020 13:17:39 +0000 (13:17 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 14:56:14 +0000 (14:56 +0000)
commit4572c2f6fc5bfd3dc1e8cf2c61f212ef62100dd8
tree3526530ea7d1ecbe5f4b29774aa57712e0076342
parent87fe04b1857f385159ff3abb9957a54a7344f94d
build,vendor: never carry around parts of differential signals.

When a port component is skipped, it should appear neither in the RTL
nor in the constraint file. However, passing around components of
differential ports explicitly makes that harder.

Fixes #456.
Supersedes #457.

Co-authored-by: Jean THOMAS <git0@pub.jeanthomas.me>
nmigen/build/plat.py
nmigen/build/res.py
nmigen/test/test_build_res.py
nmigen/vendor/intel.py
nmigen/vendor/lattice_ecp5.py
nmigen/vendor/lattice_ice40.py
nmigen/vendor/lattice_machxo_2_3l.py
nmigen/vendor/xilinx_7series.py
nmigen/vendor/xilinx_spartan_3_6.py
nmigen/vendor/xilinx_ultrascale.py