Support for 'modports' for System Verilog interfaces
authorRuben Undheim <ruben.undheim@gmail.com>
Fri, 12 Oct 2018 18:58:37 +0000 (20:58 +0200)
committerRuben Undheim <ruben.undheim@gmail.com>
Fri, 12 Oct 2018 19:11:48 +0000 (21:11 +0200)
commit458a94059e6738d93a87ddb9af282d0e1d28791d
tree7d2e8430a312360dd5d7049850b5493eb1dc1734
parent75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1
Support for 'modports' for System Verilog interfaces
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/verilog/verilog_parser.y
kernel/rtlil.cc
kernel/rtlil.h
passes/hierarchy/hierarchy.cc
tests/simple/svinterface1.sv