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(parent: 4e49772) | patch
back.rtlil: only translate switch tests once.
authorwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 07:17:33 +0000 (07:17 +0000)
committerwhitequark <whitequark@whitequark.org>
Sun, 23 Dec 2018 07:17:52 +0000 (07:17 +0000)
commit45a474788cbaed361b4ad8c31aed607da28f1d14
tree57d665fd639ad32fa6f6ab20ea6e5bc96fd863d0tree
parent4e49772f67f7d30d41f14952033c0529a817f451commit | diff
back.rtlil: only translate switch tests once.

This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.
nmigen/back/rtlil.py diff | blob | history