i965: dump scheduling cycle estimates
authorConnor Abbott <cwabbott0@gmail.com>
Sat, 6 Jun 2015 14:55:21 +0000 (10:55 -0400)
committerConnor Abbott <cwabbott0@gmail.com>
Fri, 30 Oct 2015 06:19:24 +0000 (02:19 -0400)
commit45cd76e342d1e8ecea38e2048b96cf5be3a30fab
treee5a62c00c52b27d9dd7d21a55a2c25c72041f499
parent486268bdb03a36faf09d84e0458ff49dd1325c40
i965: dump scheduling cycle estimates

The heuristic we're using is rather lame, since it assumes everything is
non-uniform and loops execute 10 times, but it should be enough for
measuring improvements in the scheduler that don't result in a change in
the number of instructions.

v2:
- Switch loops and cycle counts to be compatible with older shader-db.
- Make loop heuristic 10x to match with spilling code.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
src/mesa/drivers/dri/i965/brw_cfg.h
src/mesa/drivers/dri/i965/brw_fs_generator.cpp
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp