Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings
authorenjoy-digital <florent@enjoy-digital.fr>
Sat, 25 Apr 2020 06:27:00 +0000 (08:27 +0200)
committerGitHub <noreply@github.com>
Sat, 25 Apr 2020 06:27:00 +0000 (08:27 +0200)
commit4608bd1864aae0c7a636334e0f6c1c51be51cb5d
tree0a7d65dfbfef2ac1c5ad2cde5de404917dfc6535
parent0b3c4b50fa99cd92ba83ea64a1386b94195a35d4
parentb0f8ee987667e4517574ff590f5baff336bfb9d7
Merge pull request #470 from antmicro/jboc/sdram-eeprom-timings

litex_sim: add option to create SDRAM module from SPD data