mem: Fix MSHR assert triggering for invalidated prefetches
authorSascha Bischoff <sascha.bischoff@arm.com>
Tue, 21 Feb 2017 14:14:44 +0000 (14:14 +0000)
committerSascha Bischoff <sascha.bischoff@arm.com>
Tue, 21 Feb 2017 14:14:44 +0000 (14:14 +0000)
commit46b4c402779cd8fa37bde8de0069b80bfdaa8454
tree25d9c3eb2e387d03d961f080024502839ce874e5
parent767aed453420fcf6c1fa0611a122a8636bf71003
mem: Fix MSHR assert triggering for invalidated prefetches

This changeset updates an assert in src/mem/cache/mshr.cc which was
erroneously catching invalidated prefetch requests. These requests can
become invalidated if another component writes (an exclusive access)
to this location during the time that the read request is in
flight. The original assert made the assumption that these cases can
only occur for reads generated by the CPU, and hence
prefetcher-generated requests would sometimes trip the assert.

Change-Id: If4f043273a688c2bab8f7a641192a2b583e7b20e
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
src/mem/cache/mshr.cc