i965/nir: Sort uniforms direct-first and use two different uniform registers
authorJason Ekstrand <jason.ekstrand@intel.com>
Wed, 18 Mar 2015 22:18:54 +0000 (15:18 -0700)
committerJason Ekstrand <jason.ekstrand@intel.com>
Thu, 19 Mar 2015 20:18:39 +0000 (13:18 -0700)
commit46c35c61e9c5c1b56fdd9fcd4eb45591dd16d21d
treed953302d05c0737e651c104d6632def6a51994be
parent8a33f95b7a1128b5e46bd30306961bac72f5f12e
i965/nir: Sort uniforms direct-first and use two different uniform registers

Previously, we put all the uniforms into one big array.  The problem with
this approach is that, as soon as there was one indirect array acces, the
backend would decide that the entire large array should be pull constants.
This commit splits the array in half: first direct-only uniforms and then
potentially-indirect uniforms.  This may not be optimal, but it does let
the backend promote things to push constants.

Shader-db results on HSW:
total instructions in shared programs: 4114840 -> 4112172 (-0.06%)
instructions in affected programs:     43316 -> 40648 (-6.16%)
helped:                                116
HURT:                                  0

v2: Set param_size[num_direct_uniforms] only if we have indirect uniforms.
    This caused a bug that, strangely enough, only showed up on Broadwell
    vertex shaders.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
src/mesa/drivers/dri/i965/brw_fs.h
src/mesa/drivers/dri/i965/brw_fs_nir.cpp